(A) Field of the Invention
The present invention relates to a data sensing method for dynamic random access memory (DRAM), and more particularly, to a data sensing method that improves the sensing margin for DRAM.
(B) Description of the Related Art
While a static random access memory (SRAM) cell needs six transistors for storing one bit, a DRAM cell needs only one transistor and one capacitor for achieving the same, and therefore both the chip size and cost are reduced when utilizing a DRAM for storage purposes. On the other hand, because the charges stored in the capacitor of the DRAM cell will leak over time, a periodic refresh operation is required to assure the correctness of the stored data.
FIG. 1 illustrates a schematic view of a memory cell 10 of a DRAM according to the prior art. The memory cell 10 comprises a transistor 20 (e.g. an NMOS transistor) and a storage capacitor 30 configured to store one bit of data. The capacitor 30 comprises an upper plate (first node) 32 and a lower plate (second node) 34 connected to a cell plate 26. One terminal of the transistor 20 is connected to a bit line 14 through a node 22, and the other terminal of the transistor 20 is connected to the upper plate 32 of the capacitor 30 through a storage node 24. A voltage applied to a word line 12 of the transistor 20 controls the turn-on and turn-off of the transistor 20.
The voltage of the lower plate 34 of the capacitor 30 is one-half of a supply voltage Vcc, i.e., Vcc/2. When the stored data is 1, the voltage at the storage node 24 is Vcc. When the stored data is 0, the voltage at the storage node 24 is 0. When the memory cell 10 is to be read or refreshed, the voltage at the bit line 14 is then pre-charged to Vcc/2. Subsequently, the voltage at the word line 12 is raised to a high voltage to turn on the transistor 20 such that a charge sharing process occurs between the capacitor 30 and the parasitic capacitor 40 of the bit line 14.
If the stored data is 1, the charge sharing process will cause the voltage of the bit line 14 to be greater than Vcc/2; otherwise, the voltage of the bit line 14 will be smaller than Vcc/2. A sense amplifier 16 connected to the bit line 14 senses the voltages of the bit line 14 and a reference bit line 14′ to determine the stored data, which is then rewritten into the memory cell 10 such that the data is refreshed.
The amount of voltage difference Vs of the bit line 14 after the charge sharing process can be represented as:
  Vs  =            1      2        ⁢          Vcc              (                  1          +                      Cb            Cs                          )            
wherein Cb denotes the amount of charges stored on the parasitic capacitor 40, and Cs denotes the amount of charges stored on the storage capacitor 30. In other words, as the storage capacitor 30 stores more charges, the voltage difference Vs increases. For the memory cell 10 to operate normally, the voltage difference Vs is required to be larger than the minimum sense voltage of the sense amplifier 16.
More specifically, the transistor 20 will be turned on regardless of the data, 1 or 0, stored on the capacitor 30. Conventional data sensing method for DRAM divides the sensing margin equally between these two states. Practically, however, the sensing margin is decreased owing to the variation of the voltage difference Vs caused by coupling noise, offset noise and the leakage of the capacitor 30. Particularly, as modern electronic devices place more emphasis on low power consumption, the supply voltage Vcc continues to become lower such that the sensing margin of conventional data sensing method for DRAM continues to decrease, and the error percentage thereof is growing accordingly.
Therefore, there is a need to design a mechanism to enhance the sensing margin of modern DRAMs under low supply voltage such that when accessed, the error percentage thereof can be stabilized or even reduced.